An EDA tool for generating automatically Testbenches used in VLSI System-Level Thermal Simulation

In the electronic design automation field, temperature is a critical property of smart systems, due to its impact on reliability and to its inter-dependence with power consumption. Therefore, the thermal-aware design becomes very important in the whole VLSI design phase, especially the system-level architectural thermal simulation in the initial design phase.

After you derive one system-level circuit-equivalent thermal model of your VLSI design, you also need the test stimuli to active thermal simulation for collecting thermal distribution on your design or instantaneous temperature information of each component in your design. Consequently, a good testbench is also a significant point in the whole thermal simulator.

I developed one fully automatic EDA tool for generating testbenches used in the system-level thermal simulation, the github repository address is : https://github.com/yukai622/Testbenches-for-FAST-ATSimulator , I write very detailed introduction and HOWTO instructions in the README files are located in each level folders.

Such open source project is implemented by SystemC-AMS, SystemC-AMS is the extension of the SystemC framework for modelling analog and mixed-signal systems. Its role is to provide a higher level view of AMS systems so as to allow early simulation and validation of the overall system.

The SystemC-AMS thermal simulator is connected to a testbench module having an interface complementary to the that of the thermal network, power ports are in output, and temperature ports are in input. The testbench generates stimuli over time for the thermal simulator, by adopting the two possible strategies shown in the bottom box of below figure.

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This tool implement the option (a), concerning the option (b), please read the Readme file in the repository, it is involved in another project which cannot be open source for some reasons.

All the codes source published in here : https://github.com/yukai622/Testbenches-for-FAST-ATSimulator/tree/master/Generate_testbench/Block_mode/src

The codes can generate two different testbenches which related two different kinds of thermal simulation: steady and transient thermal simulations.

Steady state analysis determines the temperature distribution based on a power density distribution that does not change over time, by assuming either typical power values (i.e., average power) or worst case scenarios (i.e., maximum power consumption). This kind of analysis is thus useful to make preliminary design exploration, e.g., to guide floorplanning or to make quick leakage estimations. On the contrary, transient analysis focuses on the temporal response to time varying conditions, that is especially crucial to evaluate reliability effects. Accumulated heat can indeed determine peak temperatures much higher than the average values. Additionally, thermal stress strictly depends on thermal cycling and on the length of the peak temperature periods. As a result, transient simulation allows to gather a more complete estimation of the evolving circuit conditions, and allows to consider temperature as an additional design dimension.

Since the generated testbenches will occupy too much space in here, I uploaded all different kinds of testbenches in here : https://github.com/yukai622/Testbenches-for-FAST-ATSimulator/tree/master/Generate_testbench/Block_mode .
Please go there to check it.

To verify the project is belonged to me, the below figures show the synchronized github account in my utopian-io website. The account name is same as the owner of such project shown in the github website.

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Posted on Utopian.io - Rewarding Open Source Contributors

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