First open-source simulation framework for the assessment of aging effects in SoC designs

In deeply scaled CMOS technologies, device aging causes transistor performance parameters to degrade over time. While reliable models to accurately assess these degradations are available for devices and circuits, the extension to these models for estimating the aging of microprocessor cores is not trivial and there is no well accepted model in the open source community.

Therefore, our team want to open source of our developed simulation framework for the assessment of aging effects in SoC designs, namely Vintage developed by TCL language. It should be the first open source simulator for investigating NBTI aging effects of SoC design s in electronic design automation(EDA) field.

This is the github repository address of our framework: https://github.com/yukai622/Vintage , please go there for more information of our framework and the instructions of how to use our framework. There is a very detailed Readme file describes our framework, you also can check our papers which illustrate our proposed framework. In EDA field, there is no opensource gate-level aging simulator in the community according to our knowledge, we want to help designers or people in academic field can conduct aging degradation simulation of SoC for free.

Vintage is a plugin of Synopsys PrimeTime for calculating the NBTI-induced aging. Vintage uses aging-characterized libraries to calculate gate-by-gate aging on a critical path. Since most conventional design kits do not provide designers with aging library that account for time-dependent variations, Vintage implements a SPICE-based flow for the analysis of the aging of CMOS library cells to achieve such aging library. Vintage is a comprehensive solution for the assessment of NBTI induced aging effects in System-on-Chip designs. It consists of a Static Simulation Framework which tracks the aging of powermanaged logic circuits and SRAM memory arrays, and provides accurate estimation of the life-time of microprocessor-based designs. Easy to integrate into state-of-the-art tools, VintAge represents the enabling technology for future design flows in which aging is included in the optimization loop at any level of abstraction, from application and system level down to circuit and gate level.

Above figure illustrates the mechanism of Vintage, it consists of a static timing analysis (STA) engine, which takes as inputs a synthesized design (i.e., a verilog) of which life-time estimation is required, a test-bench that emulates the real work-load, and a technology file characterized for aging. From these information, depending on the operating condition defined by the user, VintAge extracts & annotates the aging of each unit into the design database. The new aging information are then used for the estimation of the circuit lifetime.

Example

If we select an open source synthesizable microprocessor core, namely PLASMA. When using Vintage to investigate the aging degradation of the core, the whole framework is shown in below figure.

Assume the fresh PLASMA core max operating frequency is 350MHz, we can use our developed simulation framework derive the aging of its max operating frequency profile in 10 years as shown in below figure. More important, our developed framework can run any kind of real application on the core to imitate real working condition since it is a system-level platform but computing aging degradation of each gate in your design.

For more information, please check my github repository : https://github.com/yukai622/Vintage

To verify the project is belonged to me, the below figures show the synchronized github account in my utopian-io website. The account name is same as the owner of such project shown in the github website.

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